In the self-synchronizing digital communication system, the methods to extract the bit synchronized signal mainly includes filtering method, enveloping “collapse” method, and DPLL (Digital Phase-Locked Loop) method. The self-synchronization method extracts the synchronization information from the code in the receiving end without inserting the pilot signal at the transmitter end, making it the most commonly used method in modern digital communication. The process of extracting the timing pulse sequence is called bit synchronization, which is implemented by an external or a self-synchronization method. In digital communication systems, information is transmitted in a series of code sequences the receiver must know the starting and ending time of each code, so it needs to have a bit timing pulse sequence for the sampling decision, which has the same repetition frequency as the code rate of transmit end and the same phase as the optimal decision time. The results show that the improved system performs the accurate extraction of bit synchronized clock, reduces the phase jitter problem, improves the system running efficiency and the ability of anti-interference, and guarantees the synchronization performance of the digital communication system. The design is completed by using FPGA chip and VHDL hardware description language and performs the simulation verification on Quartus II. By using a newly added digital filter between the phase detector and the controller, the phase difference pulses from the phase detector are counted and processed, before being transmitted to the controller for adjusting the phase of the output clock. Clock synchronization enables devices to trace a clock source to synchronize frequencies.An improved method is proposed in this design to reduce the phase jitter after the synchronization or the random noise induced phase jitter in a bit synchronization clock extraction circuit. Time synchronization enables devices to receive discontinuous time reference information and to adjust their times to synchronize times. The phase of this clock is represented by a moment in the form of year, month, day, hour, minute, second, millisecond, microsecond, and nanosecond. When a time is adjusted, both the frequency and phase of a clockĪre adjusted. The working principle of time synchronization is similar to that of clock synchronization. Time synchronization adjusts the internal clocks and moments of devices based on a received time. A moment is a transient in a period, whereas a time interval is the interval between two transients. Generally, the word "time" indicates either a moment or a time interval. Time synchronization, also called phase synchronization Clock synchronization enables the clocks on the sender and receiver to be synchronized. ![]() ![]() The clocks on the sender and receiver must also be synchronized to ensure smooth communication. Timeslot to ensure that the sender and receiver communicate properly. A receiver needs to extract this pulse signal from this specific On a digital communication network, a sender places a pulse signal in a specific timeslot for transmission. In this manner, all devices on a network run at the same rate. ![]() Signals are transmitted at the same average rate within the valid time. ![]() Synchronization is classified into the following types:Ĭlock synchronization, also called frequency synchronizationĬlock synchronization maintains a strict relationship between signal frequencies or between signal phases.
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